Descriere: CADENCE LIRARIES/INTRFC MAINT
Descriere: UNIVER DESIGN SYS VWDRAW/VIEWSIM
Descriere: ATMEL SYNARIO BASIC PACKAGE
Descriere: INTEGRAPH SCHEM SYNTH/SIM LIBRA
Descriere: CADENCE VERILOG LIB/INTRFC MAINT
Descriere: FPGA VIEWLOGIC-BASED INTRMED UPG
Descriere: FPGA VIEWLOGIC-BASED INTRMED UPG
Descriere: FPGA DESIGN SYS W/VWDRAW/VIEWSIM
Descriere: ATMEL SYNARIO VHDL SYNTHESIS OPT
Descriere: FPGA DESIGN SYS W/VWDRAW/VIEWSIM
Descriere: FPGA DESIGN SYSTEM W/VIEWDRAW
Descriere: UNIV AT6000 PHYSICAL DESIGN SYS
Descriere: ATMEL SYNARIO VERILOG SIM OPTION
Descriere: ATMEL SYNARIO VHDL SYNTHESIS OPT
Descriere: INTEGRAPH SCHEM SYNTH/SIM LIBRA
Descriere: DESIGN SYS PWRVW SCHEMATIC ENTRY
Descriere: INTEGRAPH SCHEM SYNTH/SIM MAINT
2025/05/20